(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming planarized shallow trench isolation structures in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Shallow trench isolation (STI) is now commonly used in the art as an alternative to local oxidation of silicon (LOCOS) for forming isolations between active device areas in the integrated circuit. STI offers the advantages of smaller isolation area and better surface planarization when compared to LOCOS. However, the STI process suffers from dishing, especially over large trenches. Dishing can cause excessive device leakage in some cases. Currently, reverse masking, dummy active areas, and a newer nitride cap are the most commonly employed methods to prevent dishing during the STI chemical mechanical polishing (CMP) process. Unfortunately, these processes are expensive and time consuming. Furthermore, CMP is a “dirty” process that needs many subsequent cleaning steps. If CMP could be eliminated, many trench isolation problems could be solved.
Co-pending U.S. patent application Ser. No. 09/439,357 (CS-99-059) to James Lee, filed on Nov. 15, 1999, now U.S. Pat. No. 6,197,691, teaches a new technique for preventing dishing in an STI process. This process requires an additional HF dip step. Co-pending U.S. patent application Ser. No. 09/803,187 (CS-00-138) to V. L. S. Keong et al, filed on Mar. 12, 2001, is an improvement over U.S. Pat. No. 6,197,691 where the HF dip step is not required. Several prior art approaches disclose methods to form and planarize shallow trench isolations. U.S. Pat. No. 6,057,210 to Yang et al shows a process in which corners of the silicon nitride areas are exposed using a wet etch. U.S. Pat. No. 6,015,755 to Chen et al shows a partial reverse mask process in which a reverse mask is formed over wide areas. CMP or etchback is used. U.S. Pat. Nos. 4,954,459 to Avanzino et al and 5,961,794 to Morita teach reverse mask processes. U.S. Pat. Nos. 5,923,993 to Sahota, 6,057,207 to Lin et al, and 6,103,581 to Lin et al teach CMP processes. U.S. Pat. No. 6,004,863 discloses isotropic etching of oxide peaks.